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K4H561638H
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
256Mb H-die DDR SDRAM Specification
66 TSOP-II & 60 FBGA
Industrial Temp. -40 to 85C
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Rev. 1.2 January 2006
K4H561638H Table of Contents
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
1.0 Key Features ...............................................................................................................................4 2.0 Ordering Information ...................................................................................................................4 3.0 Operating Frequencies................................................................................................................4 4.0 Pin Description ............................................................................................................................5 5.0 Package Physical Dimension .....................................................................................................6 6.0 Block Diagram (4Mbit x16 I/O x4 Banks) ...................................................................................7 7.0 Input/Output Function Description ............................................................................................8 8.0 Command Truth Table.................................................................................................................9 9.0 General Description...................................................................................................................10 10.0 Absolute Maximum Rating .....................................................................................................10 11.0 DC Operating Conditions ........................................................................................................10 12.0 DDR SDRAM Spec Items & Test Conditions .........................................................................11 13.0 Input/Output Capacitance ......................................................................................................11 14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A ......................................................12 15.0 DDR SDRAM IDD spec table ..................................................................................................13 16.0 AC Operating Conditions .......................................................................................................14 17.0 AC Overshoot/Undershoot specification for Address and Control Pins............................14 18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins...............................15 19.0 AC Timming Parameters & Specifications ...........................................................................16 20.0 System Characteristics for DDR SDRAM ..............................................................................17 21.0 Component Notes ....................................................................................................................18 22.0 System Notes ...........................................................................................................................20 23.0 IBIS : I/V Characteristics for Input and Output Buffers ........................................................21
Rev. 1.2 January 2006
K4H561638H Revision History
Revision 1.0 1.1 1.2 Month May September January Year 2006 2006 2007
Only for Aisin-AW
History - First release - Added DDR400 speed bin
Preliminary Industrial DDR SDRAM
- Revised overshoot/undershoot specification following JEDEC SPEC - Added tPDEX on AC parameter specification
Rev. 1.2 January 2006
K4H561638H 1.0 Key Features
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
* VDD : 2.5V 0.2V, VDDQ : 2.5V 0.2V for DDR266, 333 * VDD : 2.6V 0.1V, VDDQ : 2.6V 0.1V for DDR400 * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe [L(U)DQS] (x16) * Four banks operation * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * MRS cycle with address key programs -. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock) -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) * All inputs except data & DM are sampled at the positive going edge of the system clock(CK) * Data I/O transactions on both edges of data strobe * Edge aligned data output, center aligned data input * LDM,UDM for write masking only (x16) * Auto & Self refresh * 7.8us refresh interval(8K/64ms refresh) * Support Industrial Temp (-40 to 85C) * Maximum burst refresh cycle : 8 * 66pin TSOP II, 60Ball FBGA Pb-Free(RoHS compliant) package
2.0 Ordering Information
Part No. K4H561638H-UI/PCC K4H561638H-UI/PB3 K4H561638H-UI/PB0 K4H561638H-ZI/PB3 K4H561638H-ZI/PB0 16M x 16 16M x 16 Org. Max Freq. CC(DDR400@CL=3.0) B3(DDR333@CL=2.5) B0(DDR266@CL=2.5) B3(DDR333@CL=2.5) B0(DDR266@CL=2.5) SSTL2 60 FBGA SSTL2 66pin TSOP II Interface Package
3.0 Operating Frequencies
B3(DDR333@CL=2.5) Speed @CL2 Speed @CL2.5 Speed @CL3 CL-tRCD-tRP 133MHz 166MHz 2.5-3-3 A2(DDR266@CL=2.0) 133MHz 133MHz 2-3-3 B0(DDR266@CL=2.5) 100MHz 133MHz 2.5-3-3
Rev. 1.2 January 2006
K4H561638H 4.0 Pin Description
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
16Mb x 16
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
66 65 64 63 62 61 60 59 58
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
66Pin TSOPII (400mil x 875mil) (0.65mm Pin Pitch) Bank Address BA0~BA1 Auto Precharge A10
57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
256Mb TSOP-II Package Pinout
16M x 16
1 2 3 7 8 9 VSSQ DQ15 VSS A VDD DQ0 VDDQ DQ14 VDDQ DQ13 B DQ2 VSSQ DQ1 DQ12 VSSQ DQ11 C DQ4 VDDQ DQ3 DQ10 VDDQ DQ9 D DQ6 VSSQ DQ5 DQ8 VSSQ UDQS E LDQS VDDQ DQ7 VREF VSS UDM F LDM VDD NC CK CK G WE CAS A12 CKE H RAS CS A11 A9 J BA1 BA0 A8 A7 K A0 A10/AP A6 A5 L A2 A1 A4 VSS M VDD A3
Note : 1. In case of only 8 or 4 DQs out of 16 DQs are used, UDQS and DQ0~7 must be used.
Organization 16Mx16
Row Address A0~A12
Column Address A0-A8
DM is internally loaded to match DQ and DQS identically. Row & Column address configuration
Rev. 1.2 January 2006
K4H561638H
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
5.0 Package Physical Dimension
Units : Millimeters
(0.80) (0.50) (10x) (10x) 0.125 +0.075 -0.035 (0.50) 0x~8x 5.50 1.00 x 11 = 11.00
(R 0.
0 .2 5)
#66
#34
10.160.10
(1.50)
#1 (1.50)
#33
0.6650.05
0.2100.05
(0.80)
1.000.10
15
0.05 MIN
(R 0.
[
0.075 MAX ]
(10x)
NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS'Y OUT QUALITY
66pin TSOPII / Package dimension
Units : Millimeters
8.00 0.10 0.10 Max 0.80 x 8 = 6.40 ENCAPSULANT AREA 0.80 x 4 = 3.20 1.60 9 8 7 6 5 1.60 4 3 2 1 0.80 1.00 A B C 0.50 D 14.00 0.10 E 14.0 0.10 F G 0.45 0.05 0.50 5.50 H J K L M
8.0 0 0.10
(R
(0.71)
0.65TYP 0.650.08
0.300.08
0.10 MAX
( 4x
5)
)
25
)
(R
0 .1
(10x)
1.20MAX
22.220.10
0.25TYP
0.35 0.05 60 - 0.45
(0.90) 0.05 (1.80)
(0.90)
TOP VIEW
1.10 0.10
BOTTOM VIEW
60Ball FBGA Package Dimension
Rev. 1.2 January 2006
14.00 0.10
0.45~0.75
)
11.760.20
(10.16)
K4H561638H
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
6.0 Block Diagram ( 4Mb x 16 I/O x4 Banks )
x16
LWE
I/O Control
CK, CK
Data Input Register Serial to parallel
L(U)DM
Bank Select
x32
2Mx32 Output Buffer 2-bit prefetch Sense AMP Refresh Counter Row Buffer Row Decoder 2Mx32 2Mx32 2Mx32
x32 x16
x16
DQi
Address Register
CK, CK ADD
Column Decoder LCBR LRAS Col. Buffer
Latency & Burst Length Strobe Gen. DLL Data Strobe
LCKE
Programming Register LRAS LCBR LWE LCAS LWCBR CK, CK
Timing Register
DM Input Register
CK, CK
CKE
CS
RAS
CAS
WE
L(U)DM
Rev. 1.2 January 2006
K4H561638H
SYMBOL CK, CK TYPE Input
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
DESCRIPTION
7.0 Input/Output Function Description
Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE Low provides PRECHARGE POWERDOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughput READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled during POWER-DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS Low level after Vdd is applied upon 1st power up, After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH entry and exit, VREF must be maintained to this input. Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Command Inputs : RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0~D7 ; UDM corresponds to the data on DQ8~DQ15. DM may be driven high, low, or floating during READs. Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). Data Input/Output : Data bus Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0~D7 ; UDQS corresponds to the data on DQ8~DQ15. LDQS is NC on x4 and x8. No Connect : No internal electrical connection is present. DQ Power Supply : +2.5V 0.2V. (+2.6V 0.1V for DDR400) DQ Ground. Power Supply : +2.5V 0.2V. (+2.6V 0.1V for DDR400) Ground. SSTL_2 reference voltage.
CKE
Input
CS RAS, CAS, WE
Input Input
LDM,(UDM)
Input
BA0, BA1
Input
A [0 : 12]
Input
DQ
I/O
LDQS,(U)DQS
I/O
NC VDDQ VSSQ VDD VSS VREF
Supply Supply Supply Supply Input
Rev. 1.2 January 2006
K4H561638H
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low) CAS L L L H X H L L H H X V X X H X V X H WE L L H H X H H L L L X V X X H X V X X H X 8 9 9 X X V X L H V V V L H L H X X BA0,1 A10/AP A0 ~ A9, A11 ~ A12 Note 1, 2 1, 2 3 3 3 3 4 4 4 4, 6 7 5
8.0 Command Truth Table
COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Self Refresh Entry Exit CKEn-1 CKEn H H H L H H H H Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DM(UDM/LDM for x16 only) No operation (NOP) : Not defined L H H X H L H H H L H X X H L H X X X X X L H L CS L L L L H L L L L L H L X H L H L RAS L L L H X L H H H L X V X X H X V X X H
OP CODE OP CODE X X Row Address
Column Address Column Address
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
Active Power Down
Note : 1. OP Code : Operand Code. A0 ~ A12& BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges (Write UDM/LDM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 1.2 January 2006
K4H561638H
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
4M x 16Bit x 4 Banks Double Data Rate SDRAM
9.0 General Description
The K4H561638H is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 4,194,304 words by 16bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
10.0 Absolute Maximum Rating
Parameter Voltage on any pin relative to VSS Voltage on VDD & VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 1.5 50 Unit V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
11.0 DC Operating Conditions
Parameter
Recommended operating conditions(Voltage referenced to VSS=0V, TA=-40 to 85C)
Symbol
VDD VDD VDDQ VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VI(Ratio) II IOZ IOH IOL IOH IOL
Min
2.3 2.5 2.3 2.5 0.49*VDDQ VREF-0.04 VREF+0.15 -0.3 -0.3 0.36 0.71 -2 -5 -16.8 16.8 -9 9
Max
2.7 2.7 2.7 2.7 0.51*VDDQ VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 1.4 2 5
Unit
V V V V V V V V V V uA uA mA mA mA mA
Note
Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333) Supply voltage(for device with a nominal VDD of 2.6V for DDR400) I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333) I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR400) I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs V-I Matching: Pullup to Pulldown Current Ratio Input leakage current Output leakage current Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
1 2
3 4
Note : 1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not exceed +/-2% of the dc value. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.
Rev. 1.2 January 2006
K4H561638H
Only for Aisin-AW
Conditions
Preliminary Industrial DDR SDRAM
Symbol IDD0
12.0 DDR SDRAM Spec Items & Test Conditions
Operating current - One bank Active-Precharge; tRC=tRCmin; tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating current - One bank operation ; One bank open, BL=4, Reads - Refer to the following page for detailed test condition Precharge power-down standby current; All banks idle; power - down mode; CKE = =VIH(min);All banks idle; CKE > = VIH(min); tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS and DM Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Address and other control inputs stable at >= VIH(min) or == VIH(min); CKE>=VIH(min); one bank active; active - precharge; tRC=tRASmax; tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control inputs changing once per clock cycle; CL=2 at tCK=10ns for DDR200, CL=2 at 7.5ns for DDR266(A2), CL=2.5 at tCK=7.5ns for DDR266(B0), tCK=6ns for DDR333, CL=3 at tCK=5ns for DDR400; 50% of data changing on every transfer; lout = 0 m A Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL=2 at tCK=10ns for DDR200, CL=2 at tCK=7.5ns for DDR266(A2), CL=2.5 at tCK=7.5ns for DDR266(B0), 6ns for DDR333, 5ns for DDR400; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst Auto refresh current; tRC = tRFC(min) which is 12*tCK for DDR200 at tCK=10ns; 16*tCK for DDR266 at tCK=7.5ns; 20*tCK for DDR333 at tCK=6ns, 24*tCK for DDR400 at tCK=5ns; distributed refresh Self refresh current; CKE =< 0.2V; External clock on; tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400. Operating current - Four bank operation ; Four bank interleaving with BL=4 -Refer to the following page for detailed test condition
IDD1 IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7A
13.0 Input/Output Capacitance
Parameter
Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS,WE) Input capacitance( CK, CK ) Data & DQS input/output capacitance Input capacitance(DM for x4/8, UDM/LDM for
( TA= 25C, f=100MHz)
Symbol
CIN1 CIN2 COUT CIN3
Min TSOP
2 2 4 4
Max TSOP
3 3 5 5
FBGA
1.5 1.5 3.5 3.5
FBGA
2.5 2.5 4.5 4.5
Delta Unit Note Cap(max)
0.5 0.25 0.5 pF pF pF pF 4 4 1,2,3,4 1,2,3,4
Note : 1.These values are guaranteed by design and are tested on a sample basis only. 2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system. 3. Unused pins are tied to ground. 4. This parameteer is sampled. For DDR266 and DDR333 VDDQ = +2.5V +0.2V, VDD = +3.3V +0.3V or +0.25V+0.2V. For DDR400, VDDQ = +2.6V +0.1V, VDD = +2.6V +0.1V. For all devices, f=100MHz, tA=25C, Vout(dc) = VDDQ/2, Vout(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level).
Rev. 1.2 January 2006
K4H561638H
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A
IDD1 : Operating current: One bank operation 1. Typical Case: For DDR200,266,333: Vdd = 2.5V, T=25C; For DDR400: Vdd=2.6V,T=25C Worst Case : Vdd = 2.7V, T= 10C 2. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 3. Timing patterns - B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - A2 (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - B3(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=3*tCK, tRC = 10*tCK, tRAS=7*tCK Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing *50% of data changing at every transfer Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT
IDD7A : Operating current: Four bank operation 1. Typical Case: For DDR200,266,333: Vdd = 2.5V, T=25C; For DDR400: Vdd=2.6V,T=25C Worst Case : Vdd = 2.7V, T= 10C 2. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 4. Timing patterns - B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *50% of data changing at every burst - A2(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *50% of data changing at every burst - B3(166Mhz,CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *50% of data changing at every burst - CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing *50% of data changing at every transfer Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT
Rev. 1.2 January 2006
K4H561638H
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
(VDD=2.7V, T = 10C)
15.0 DDR SDRAM IDD spec table
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A
16Mx16 (K4H561638H) CC(DDR400@CL=3.0)
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
B3(DDR333@CL=2.5)
90 125 3 30 25 35 55 160 160 180 3 1.5 330
B0(DDR266@CL=2.5)
80 115 3 25 23 30 45 155 155 165 3 1.5 280
Unit Notes
mA mA mA mA mA mA mA mA mA mA mA mA mA
Rev. 1.2 January 2006
K4H561638H
Only for Aisin-AW
Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 Min
Preliminary Industrial DDR SDRAM
Max VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2 0.5*VDDQ-0.2 Unit V V V V 1 2 Note
16.0 AC Operating Conditions
Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs VREF + 0.31
Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
17.0 AC Overshoot/Undershoot specification for Address and Control Pins
Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to Specification DDR400 1.5 V 1.5 V 4.5 V-ns 4.5 V-ns DDR333 1.5 V 1.5 V 4.5 V-ns 4.5 V-ns DDR200/266 1.5 V 1.5 V 4.5 V-ns 4.5 V-ns
VDD 5 4 3 2 Volts (V) 1 0 -1 -2 -3 -4 -5 0
Overshoot Maximum Amplitude = 1.5V
Area
Maximum Amplitude = 1.5V
GND
0.6875 1.5 2.5 3.5 4.5 5.5 6.3125 7.0 0.5 1.0 2.0 3.0 4.0 5.0 6.0 6.5 Tims(ns) undershoot
AC overshoot/Undershoot Definition
Rev. 1.2 January 2006
K4H561638H
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
Specification DDR400 1.2 V 1.2 V 2.4 V-ns 2.4 V-ns DDR333 1.2 V 1.2 V 2.4 V-ns 2.4 V-ns DDR200/266 1.2 V 1.2 V 2.4 V-ns 2.4 V-ns
18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins
Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to
VDDQ Overshoot 5 4 3 2 Volts (V) 1 0 -1 -2 -3 -4 -5 0 0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0 Tims(ns) undershoot Maximum Amplitude = 1.2V GND Area Maximum Amplitude = 1.2V
DQ/DM/DQS AC overshoot/Undershoot Definition
Rev. 1.2 January 2006
K4H561638H
Only for Aisin-AW
CC (DDR400@CL=3.0) Min Max
55 70 40 15 15 10 15 2 tCK tCH tCL tDQSCK tAC tDQSQ tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tIS tIH tIS tIH tHZ tLZ tMRD tDS tDH tIPW tDIPW tXSNR tXSRD tREFI tQH tHP TSOP Package FBGA Package tQHS tQHS tWPST tRAP tDAL tPDEX 0.4 15 (tWR/tCK) + (tRP/tCK) 1 tHP -tQHS tCLmin or tCHmin 6 5 0.45 0.45 -0.55 -0.65 0.9 0.4 0.72 0 0.25 0.2 0.2 0.35 0.35 0.6 0.6 0.7 0.7 -0.65 -0.65 10 0.4 0.4 2.2 1.75 75 200 7.8 0.5 0.6 0.4 18 (tWR/tCK) + (tRP/tCK) 1 tHP -tQHS tCLmin or tCHmin +0.65 +0.65 12 10 0.55 0.55 +0.55 +0.65 0.4 1.1 0.6 1.28 70K
Preliminary Industrial DDR SDRAM
B3 (DDR333@CL=2.5) Min Max
60 72 42 18 18 12 15 1 7.5 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.75 0.75 0.8 0.8 -0.7 -0.7 12 0.45 0.45 2.2 1.75 75 200 7.8 0.55 0.5 0.6 0.4 20 (tWR/tCK) + (tRP/tCK) 1 tCK tCK 23 tHP -tQHS tCLmin or tCHmin +0.7 +0.7 12 12 0.55 0.55 +0.6 +0.7 0.45 0.4 1.1 0.6 1.25 70K
19.0 AC Timming Parameters & Specifications
Parameter
Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command CL=2.0 Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width Address and Control Input setup time(fast) Address and Control Input hold time(fast) Address and Control Input setup Address and Control Input hold time(slow) Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time Power Down Exit Time TSOP Package FBGA Package CL=2.5 CL=3.0
Symbol
tRC tRFC tRAS tRCD tRP tRRD tWR tWTR
B0 (DDR266@CL=2.5) Min Max
65 75 45 20 20 15 15 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 1.0 1.0 -0.75 -0.75 15 0.5 0.5 2.2 1.75 75 200 7.8 0.75 0.75 0.6 +0.75 +0.75 12 12 0.55 0.55 +0.75 +0.75 0.5 0.5 1.1 0.6 1.25 70K
Unit
ns ns ns ns ns ns ns tCK ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns tCK us ns ns ns tCK
Note
22
13
15, 17~19 15, 17~19
16~19 16~19 11 11 j, k j, k 18 18
14 21 20, 21 21 12
Rev. 1.2 January 2006
K4H561638H
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
20.0 System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR333, DDR266 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS PARAMETER DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) SYMBOL DCSLEW DDR400 MIN 0.5 MAX 4.0 DDR333 MIN 0.5 MAX 4.0 DDR266 MIN 0.5 MAX 4.0 Units V/ns Notes a, m
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns tIS 0 +50 +100 tIH 0 0 0 Units ps ps ps Notes i i i
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns tDS 0 +75 +150 tDH 0 +75 +150 Units ps ps ps Notes k k k
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate +/- 0.0 V/ns +/- 0.25 V/ns +/- 0.5 V/ns tDS 0 +50 +100 tDH 0 +50 +100 Units ps ps ps Notes j j j
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 1.0 1.0 Maximum (V/ns) 4.5 4.5 Notes a,c,d,f,g,h b,c,d,f,g,h
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 0.7 0.7 Maximum (V/ns) 5.0 5.0 Notes a,c,d,f,g,h b,c,d,f,g,h
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS PARAMETER Output Slew Rate Matching Ratio (Pullup to Pulldown) DDR400 MIN 0.67 MAX 1.5 DDR333 MIN 0.67 MAX 1.5 DDR266 MIN 0.67 MAX 1.5 Notes e,m
Rev. 1.2 January 2006
K4H561638H
1. All voltages referenced to Vss.
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
21.0 Component Notes
2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). VDDQ 50 Output (Vout) 30pF
Figure 1 : Timing Reference Load 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac). 5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level. 6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.2VDDQ is recognized as LOW. 7. Enables on.chip refresh and address counters. 8. IDD specifications are tested after the device is properly initialized. 9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK, is VREF. 10. The output timing reference voltage level is VTT. 11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). 12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance (bus turnaround) will degrade accordingly. 13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will be transitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 15. For command/address input slew rate 1.0 V/ns 16. For command/address input slew rate 0.5 V/ns and < 1.0 V/ns
Rev. 1.2 January 2006
K4H561638H
Component Notes
17. For CK & CK slew rate 1.0 V/ns
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 19. Slew Rate is measured between VOH(ac) and VOL(ac). 20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. 21. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and pchannel to n-channel variation of the output drivers.
22. tDQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 23. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266 at CL=2.5 and tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks
Rev. 1.2 January 2006
K4H561638H 22.0 System Notes
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2. Test point Output 50 VSSQ Figure 2 : Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 3. VDDQ 50 Output Test point Figure 3 : Pulldown slew rate test load c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. d. Evaluation conditions Typical : 25 C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process Minimum : 70 C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process Maximum : 0 C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. Verified under typical conditions for qualification purposes. g. TSOPII package divices only. h. Only intended for operation up to 400 Mbps per pin. i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotonic.
Rev. 1.2 January 2006
K4H561638H
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
23.0 IBIS : I/V Characteristics for Input and Output Buffers
DDR SDRAM Output Driver V-I Characteristics
DDR SDRAM Output driver characteristics are defined for full and half strength operation as selected by the EMRS bit A1. Figures 3 and 4 show the driver characteristics graphically, and tables 8 and 9 show the same data in tabular format suitable for input into simulation tools. The driver characteristcs evaluation conditions are: Typical Minimum Maximum 25xC 70xC 0xC Vdd/Vddq = 2.5V, typical process Vdd/Vddq = 2.3V, slow-slow process Vdd/Vddq = 2.7V, fast-fast process
Output Driver Characteristic Curves Notes:
1. The full variation in driver current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure 3 and 4. 2. It is recommended that the "typical" IBIS V-I curve lie within the inner bounding lines of the V-I curves of Figure 3 and 4. 3. The full variation in the ratio of the "typical" IBIS pullup to "typical" IBIS pulldown current should be unity +/- 10%, for device drain to source voltages from 0.1 to1.0. This specification is a design objective only. It is not guaranteed.
160
Iout(mA)
140 120 100 80 60 40 20 0
0.0 0.5 1.0 1.5 2.0 2.5
Maximum Typical High Typical Low Minimum
Pullup Characteristics for Full Strength Output Driver
Vout(V)
0 .0 0 -20 -40
1 .0
2 .0
Iout(mA)
-60 -80 -100 -120 -140 -160 -180 -200 -220
Minumum Typical Low
Typical High Maximum
Pulldown Characteristics for Full Strength Output Driver
Vout(V)
Figure 3. I/V characteristics for input/output buffers:Pull up(above) and pull down(below)
Rev. 1.2 January 2006
K4H561638H
Only for Aisin-AW
Pulldown Current (mA)
Preliminary Industrial DDR SDRAM
pullup Current (mA)
Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7
Typical
Low 6.0 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.9 63.3 63.8 64.1 64.6 64.8 65.0
Typical
High 6.8 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4
Minimum 4.6 9.2 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5
Maximum 9.6 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8
Typical
Low -6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -41.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5 -52.7 -52.8
Typical
High -7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -155.3 -160.1
Minimum -4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -41.1 -41.2
Maximum -10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6 -192.9 -198.2
Table 8. Full Strength Driver Characteristics
Rev. 1.2 January 2006
K4H561638H
90 80 70 60
Only for Aisin-AW
Preliminary Industrial DDR SDRAM
Maximum Typical High Typical Low Minimum
Iout(mA)
50
Iout(mA)
40 30 20 10 0 0.0 1.0 2.0
Pullup Characteristics for Weak Output Driver
Vout(V)
0.0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90
1.0
2.0
Iout(mA)
Minumum Typical Low
Typical High Maximum
Pulldown Characteristics for Weak Output Driver
Vout(V)
Figure 4. I/V characteristics for input/output buffers:Pull up(above) and pull down(below)
Rev. 1.2 January 2006
K4H561638H
Only for Aisin-AW
Pulldown Current (mA)
Preliminary Industrial DDR SDRAM
pullup Current (mA)
Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7
Typical
Low 3.4 6.9 10.3 13.6 16.9 19.6 22.3 24.7 26.9 29.0 30.6 31.8 32.8 33.5 34.0 34.3 34.5 34.8 35.1 35.4 35.6 35.8 36.1 36.3 36.5 36.7 36.8
Typical
High 3.8 7.6 11.4 15.1 18.7 22.1 25.0 28.2 31.3 34.1 36.9 39.5 42.0 44.4 46.6 48.6 50.5 52.2 53.9 55.0 56.1 57.1 57.7 58.2 58.7 59.2 59.6
Minimum 2.6 5.2 7.8 10.4 13.0 15.7 18.2 20.8 22.4 24.1 25.4 26.2 26.6 26.8 27.0 27.2 27.4 27.7 27.8 28.0 28.1 28.2 28.3 28.3 28.4 28.5 28.6
Maximum 5.0 9.9 14.6 19.2 23.6 28.0 32.2 35.8 39.5 43.2 46.7 50.0 53.1 56.1 58.7 61.4 63.5 65.6 67.7 69.8 71.6 73.3 74.9 76.4 77.7 78.8 79.7
Typical
Low -3.5 -6.9 -10.3 -13.6 -16.9 -19.4 -21.5 -23.3 -24.8 -26.0 -27.1 -27.8 -28.3 -28.6 -28.7 -28.9 -28.9 -29.0 -29.2 -29.2 -29.3 -29.5 -29.5 -29.6 -29.7 -29.8 -29.9
Typical
High -4.3 -8.2 -12.0 -15.7 -19.3 -22.9 -26.5 -30.1 -33.6 -37.1 -40.3 -43.1 -45.8 -48.4 -50.7 -52.9 -55.0 -56.8 -58.7 -60.0 -61.2 -62.4 -63.1 -63.8 -64.4 -65.1 -65.8
Minimum -2.6 -5.2 -7.8 -10.4 -13.0 -15.7 -18.2 -20.4 -21.6 -21.9 -22.1 -22.2 -22.3 -22.4 -22.6 -22.7 -22.7 -22.8 -22.9 -22.9 -23.0 -23.0 -23.1 -23.2 -23.2 -23.3 -23.3
Maximum -5.0 -9.9 -14.6 -19.2 -23.6 -28.0 -32.2 -35.8 -39.5 -43.2 -46.7 -50.0 -53.1 -56.1 -58.7 -61.4 -63.5 -65.6 -67.7 -69.8 -71.6 -73.3 -74.9 -76.4 -77.7 -78.8 -79.7
Table 9. Weak Driver Characteristics
Rev. 1.2 January 2006

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